`timescale 1ns/1ns
module main_mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	input [7:0]c,
	
	output [7:0]d
);

wire [7:0]m_a_b;
sub_mod sub_mod_1(.clk(clk),.rst_n(rst_n),.a(a),.b(b),.d(m_a_b));
wire [7:0]m_b_c;
sub_mod sub_mod_2(.clk(clk),.rst_n(rst_n),.a(b),.b(c),.d(m_b_c));
sub_mod sub_mod_3(.clk(clk),.rst_n(rst_n),.a(m_a_b),.b(m_b_c),.d(d));

endmodule

module sub_mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	
	output [7:0]d
);
reg [7:0]d_r;
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		d_r<=8'd0;
	else if(a<b)
		d_r<=a;
	else
		d_r<=b;
		
end
assign d=d_r;
endmodule